The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device suitable for a synchronous memory which synchronizes with an external clock signal. In addition, the present invention relates to a phase locked loop (PLL) for use in the semiconductor memory device or the like.
Recently, the frequency of a microprocessor (MPU) clock has increased for faster operation. A shorter cycle time for a cache memory that directly supplies data to the MPU has also been required, along with the fast operation of the MPU. In an asynchronous memory which is started to write/read data when supplied with address input, the conventional design has sought to reduce the access time to adapt to the increase of the clock frequency. However, the memory device generally has a large variation in access time due to the unevenness of power supply voltage, temperature and production process. Therefore, the conventional asynchronous memory device has needed to determine the clock period under the condition of the longest access time. This has prevented the MPU clock period from being short. Thus, as a fast memory device, the synchronous memory device which operates in synchronism with the MPU clock has lately attracted considerable attention.
As an example of means for fast operation of asynchronous memory, there is known a method for high-speed transfer of successive data by parallel reading of data to a plurality of input/output (I/O) lines, which is disclosed in JP-A-57-150190. In this memory device, at least part of successive data is outputted at a time, temporarily stored in a certain buffer region and then successively fast read from the buffer region.
A synchronous memory device is disclosed in JP-A-5-120114. This memory device has no PLL and is constructed to generate an internal common clock signal in synchronism with an external clock and supply it to the internal circuits for row address, column address and data output, thus actuating them to operate.
A synchronous memory device with PLL is also known in which the internal clock from the incorporated PLL is supplied to the address buffer and output buffer as shown in FIG. 2A. Referring to FIG. 2A, there is shown a semiconductor memory chip 1 which includes a PLL 2. The PLL 2 generates an internal clock .PHI..sub.0 in synchronism with the external clock. The internal clock .PHI..sub.0 from the PLL 2 is supplied to an address buffer 3 and an output buffer 9. When the internal clock .PHI..sub.0 is supplied to these buffers from the PLL 2, an address signal to the address buffer 3 is processed by the address buffer 3, a decoder 4, a word driver 5, data lines 6, a sense amplifier 7, a main amplifier 8 and the output buffer 9 in turn. The output buffer 9 supplies data to an external terminal (not shown) at the internal clock .PHI..sub.0 from the PLL 2. According to the semiconductor memory chip 1 of the synchronous type shown in FIG. 2A, since the data output is controlled by the clock signal, the time taken from the application of the clock to the data output can be made more constant, despite variations that might otherwise occur due to the unevenness of power supply voltage, temperature and production process. This synchronous memory device with PLL is described in, for example, Symposium on VLSI Circuits, 1993, pp. 15-16.
The above PLL is used for synchronizing the clock signal within a semiconductor IC with the external clock signal. The known structures are one type using a single ring oscillator for the oscillation circuit and the other type using an array of ring oscillators.
An example of the oscillation circuit using a ring oscillator is described as an MST (multi-stage-tapped) in "A 220 MHz Pipelined 16 Mb BICMOS SRAM with PLL Proportional Self-Timing Generator", IEEE International Solid-State Circuit Conference Digest of Technical Papers, 1994, pp.258-259. In this example, the ring oscillator is formed of a row of inverters. Signals are led out of the respective output terminals of the inverters and used to produce clock signals of desired phases.
An example of the array-type oscillator is proposed in "Precise Delay Generation Using Coupled Oscillators", IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1993, pp. 118-119. In this example, differential amplifiers are connected in an array to constitute oscillation circuits from which clocks of desired phases can be generated with high precision.
However, the conventional asynchronous memory device of the fast transfer type for successive data which uses the method of parallel reading of data onto a plurality of input/output lines (I/O lines) has the problem that a plurality of input/output lines and main amplifiers are necessary for producing data in parallel, thus incurring the increase of chip area.
In addition, the conventional synchronous memory device without PLL in which the signals in the internal circuits are processed in accordance with the internal common clock signal synchronized with the external clock takes a time of one cycle to transmit a signal through each of the address buffer, decoder, word driver and so on in turn. In this case, the total time taken is seven cycles of clock signal for the input signal to be transmitted from the address buffer to the output buffer. This is the limit.
Moreover, in the synchronous memory device with PLL mentioned above, the time necessary for a data signal to reach the output buffer 9 from when the address signal is inputted at the clock signal .PHI..sub.0 is relatively longer than that taken for the data at the output buffer 9 to be outputted therefrom at the clock .PHI..sub.0. Therefore, the process time necessary for the data signal to reach the output buffer 9 from when the address signal is inputted at the clock signal .PHI..sub.0 is much varied by the unevenness of production process, ambient temperature and power supply voltage. Thus, the clock signal cycle time t.sub.cycle is limited as described below.
As, for example, illustrated by the flow of signal in FIG. 2B, it is assumed that the above signal-process time is varied between a minimum time t.sub.a(min) and a maximum time t.sub.a(max) due to the unevenness of temperature and power supply voltage. In addition, it is assumed that under certain worst conditions of temperature and power supply voltage, after an address signal is inputted at a clock 1 and then at the next clock 2, corresponding data arrives latest at the output buffer as indicated by dotted curves b, respectively. In this case, the data arrived at the output buffer after the address is inputted at the clock 1 must be discriminated from others by using a judgement time shorter than the maximum time t.sub.a(max). Since the temperature and power supply voltage are changed by the external situations, corresponding data may arrive fastest as indicated by solid curves a. Thus, in this case, the above judgement time for the data corresponding to the address input at the clock 1 coincides with the time for the data corresponding to the address input at the clock 2, or may be decided as the data corresponding to the address input at the clock 2. Consequently, when the latest curve b of data flow corresponding to the address input at the clock 1 intersects the fastest curve a of data flow corresponding to the address input at the clock 2, data corresponding to address signals inputted at both time points cannot be discriminated from each other.
In other words, in order to distinguish between data corresponding to input address signals, the above intersection must be prevented from occurring. Thus, the cycle time t.sub.cycle of clock signal is required to meet the following condition. EQU t.sub.cycle &lt;t.sub.a(max) -t.sub.a(min) ( 1)
That is, the cycle time t.sub.cycle of the clock signal cannot be made shorter than the difference between the maximum and minimum values of the dispersion or unevenness of the time taken for the data signal to arrive at the output buffer 9 after the address signal is inputted at clock signal .PHI..sub.0, or (t.sub.a(max) -t.sub.a(min)). For this reason, the synchronous memory device shown in FIG. 2A has a limit in the reduction of the cycle time t.sub.cycle as indicated by the condition (1). Although the signal-process time is distributed due to the variation of power supply voltage and ambient temperature as described above, it is similarly dispersed when the chip used is one of the chips produced under scattered conditions, not under an equal condition.
In the synchronous memory with PLL in which the known ring oscillator is used, since the ring oscillator has m inverters connected in a ring shape, clock signals of different phases can be produced from the connection points between a plurality of inverters. However, if many signals of different phases are required, a large number of inverters must be connected, and hence the oscillation frequency of each clock signal is reduced. If the number of inverters is contrarily decreased for higher-frequency oscillation, signals of arbitrary phases cannot be produced. Therefore, the synchronous memory device with this PLL has a limited speed.
The conventional array-type oscillation circuit can generate precise clock signals of desired phases and of a higher frequency than the ring-type oscillation circuit. However, then the array-type oscillator is formed by currently available differential amplifiers, the consumption current is increased due to the steady current flowing in the differential amplifiers. This problem becomes serious, or the consumption current in all the oscillation circuit is increased, particularly when the number of differential amplifiers connected in an array is increased. Accordingly, when this PLL is used in the synchronous memory device, the consumption power is increased.